I am seeking a Datapath Design Engineer to join a global company in their unique Engineering team based in Cambridge. This is a Principal/Staff level position and requires you to play a key role in the specification, design, and verification of high-performance digital datapath logic for advanced ASIC products and IP.
This role requires strong mathematical ability, a solid understanding of digital design fundamentals, and hands-on expertise in Verilog and SystemVerilog.
To Be Considered You Must Have
* Strong background in mathematics (e.g. numerical methods, linear algebra, signal processing, or similar)
* Proven experience designing RTL using Verilog and SystemVerilog
* Solid understanding of synchronous digital design, timing, and clock-domain considerations
* Experience designing arithmetic-heavy or algorithmic datapaths.
* Floating-point or APU experience.
* Ability to reason about precision, overflow, rounding, and numerical accuracy
* Familiarity with ASIC design flows from RTL through synthesis
* Any Verification skills would be highly advantageous.
This role focuses on building new designs rather than maintaining legacy implementations, with opportunities to take technical ownership and lead projects. You will work on intellectually challenging, mathematics-driven problems and deliver new designs you can genuinely call your own.
As a top company you can expect a great benefits package which includes base, bonus and RSUs. Visa sponsorship can be given and relocation support can be provided if you are a technical match.
This role is very specific, so please ensure you have relevant experience before applying.
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