Join a cutting:edge verification team in Edinburgh, working on state:of:the:art automotive power ICs and embedded SoCs in a hybrid, innovative environment.
Job Title: Senior Digital Verification Engineer
Location: Edinburgh, Scotland (Hybrid)
Salary: Negotiable and competitive
The Opportunity
We are seeking a Senior Digital Verification Engineer to join our Design Centre in Edinburgh. You will be part of a new verification team working on gate:driver ICs and embedded SoCs for advanced automotive power applications. This is an exciting chance to work on state:of:the:art microelectronics in a collaborative, innovative environment.
Key Responsibilities
:Develop verification plans from microarchitecture specifications
:Create and maintain SystemVerilog/UVM verification environments
:Define and execute test plans, UVM:SV test environments, and functional coverage
:Analyze results, enhance coverage, and debug unexpected behavior
:Run and maintain regression suites
:Lead or participate in verification reviews
:Collaborate with System Engineering on requirements
:Build mixed:signal testbenches, checkers, and bus:functional models
:Apply constrained random verification methodologies
:Track deliverables and ensure on:time, high:quality executionQualifications and Experience
:Bachelor's or higher in Electrical/Electronic Engineering (or equivalent)
:Strong experience in SystemVerilog, UVM/OVM, Specman, Verilog, C/C++, ASM, TCL/TK, Python
:Knowledge of embedded SoC design and verification lifecycle
:Familiarity with CPU, memory, and I/O microarchitectures
:Experience with mixed:signal testbenches, behavioral models, constrained random verification, and bus:functional model development
:Ability to define tasks, track progress, and deliver quality resultsSkills and Attributes
:Strong analytical and debugging skills
:Detail:oriented and quality:focused
:Collaborative, team:oriented, with strong communication skills
If you are interested, please reach out to have a conversation and share your CV at