ASIC Design Engineer
Cambridge
Senior OR Principal Engineering level
I am seeking an experienced ASIC Design Engineer to join an innovative HW team. The work of the whole ASIC team includes Architecture, considering software/hardware trade-offs, RTL design, Verification at block and system level, FPGA platforms for software development and extended verification as well as implementation including DFT, synthesis, place and route, timing closure, and sign-off checks.
Due to growth, the company are expanding and seeking an ASIC Design Engineer to join an already talented group of Engineers.
They are looking to expand the team in Cambridge with this role and are seeking an Engineer with working autonomously.
Responsibilities
* Design, IP integration, and verification planning and execution.
* Specifying and/or configuring designs.
* Working closely with verification teams to develop plans and execute block-level and chip-level verification.
* Assisting the implementation team with constraints development and timing closure.
* Communication is key to be successful in this role.
Key skills
* Hands-on experience working on complex SoC designs.
* Experience of digital and physical silicon IP, such as processors, USB, PCIe, DDR SDRAM, Wi-Fi, SDIO/eMMC, MIPI CSI/DSI
* Experience of interconnect standards ACE, AXI, AHB, and APB
* Ability to form requirements and specify architectural features.
* Expert-level Verilog/SystemVerilog for design and verification.
* Familiarity with scripting languages.
* The following would also be useful:
The role is based on site in Cambridge with an expectation that you come into the office on a full-time basis.
On offer is a highly competitive salary and several other benefits.