Senior Physical Design Engineer (6 month contract + extension) - Semiconductor - Cambridge, UK - hybrid
Serving the global, niche technology industry from beautiful Lisbon
Join a team developing the next‑gen Mali GPU. Own full PnR flow from RTL to STA across multiple ~1.5M instance blocks. Collaborate closely with RTL designers and project teams to optimize PPA and meet milestone targets.
Key Responsibilities
* Drive physical implementation of GPU blocks (RTL to STA)
* Provide RTL feedback via Jira to resolve PPA and implementation issues
* Work with EDA vendors to troubleshoot and improve tool flows
* Plan and manage own work aligned to project timelines
* Support hierarchical design and inter‑block collaboration
* Expertise in Cadence (Genus, Innovus, Tempus, QRC, Conformal)
* Experience with Synopsys (Fusion Compiler, Formality)
* Full PnR flow: Synthesis, LEC, CLP, Floorplanning, Placement, CTS, Routing, STA
* Low power design (power gating, DVFS, UPF/CLP)
* Proficiency in scripting (TCL, Python, Perl) for flow development
Attributes
* Detail‑oriented with strong problem‑solving drive
* Excellent collaboration and communication skills
* Relevant experience in advanced nodes (N3P/N2P)
Seniority Level: Mid‑Senior
Employment Type: Contract
Industry: Semiconductor Manufacturing
Location: Cambridge, England, United Kingdom
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