Job Title: Senior Verification Engineer – RF/DSP
Job Description:
We are seeking a Senior Verification Engineer with strong expertise in RF/DSP signal-chain verification. The role focuses on driving end-to-end verification of complex DSP and RF blocks using UVM-based methodologies and advanced verification techniques. You will work closely with design and algorithm teams to validate signal-processing functionality and ensure high-quality silicon.
Key Responsibilities:
* Lead verification of RF/DSP signal-chain blocks using UVM
* Develop and maintain UVM testbenches and integrate VIPs
* Verify DSP algorithms such as FFT, FIR filters, and channelizers
* Create Python-based verification utilities and support CI/CD flows
* Collaborate with design and system teams to debug and close coverage
Required Skills & Experience:
* Strong hands-on experience with UVM and SystemVerilog
* Proven DSP verification experience (FFT, FIR, channelizers)
* Proficiency in Python scripting and CI/CD environments
* Experience with verification planning, coverage, and debug
Preferred Qualifications:
* MATLAB experience for algorithm modeling and validation