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Description
As a formal verification technical lead, you'll work to identify targets and complete formal verification for single or multiple design blocks and IPs (CPU, Cellular and Connectivity IP, Audio and Image Processing IP, Neural Networks IP, Memory/DMA Controller, Security IP, Peripheral IP, Interconnects, Power management subsystems, etc.). You will be responsible for:
1. Working with Apple's design engineers to develop a formal micro-architecture specification.
2. Formalizing the refinement from architecture to micro-architecture.
3. Developing comprehensive formal verification test plans.
4. Proving properties of the design, finding bugs, and collaborating with design teams to improve the micro-architecture.
5. Crafting innovative solutions for verifying complex design micro-architectures.
6. Developing reusable and optimized formal models and verification code bases.
7. Architecting correct-by-construction design methodologies for enhanced formal verification efficiency and productivity.
Key Qualifications
* Outstanding team leadership and communication skills, with experience collaborating with design and verification teams.
* Hands-on experience with VLSI and digital logic design and verification techniques.
* Advanced knowledge of SoC, CPU, GPU, or Cellular designs.
* Experience with formal property proofs on industrial designs.
* Deep understanding of pipeline architectures, memory/DMA controllers, out-of-order and speculative execution hardware, bus interconnects, and cache coherence mechanisms.
* Knowledge of formal verification technologies and abstraction techniques.
* Ability to interpret hardware specifications and use temporal logic assertion-based languages such as SVA or PSL.
* Experience with EDA formal tools; tool development experience is a plus.
* Proficiency in scripting languages and debugging skills.
* Excellent interpersonal skills and a passion for developing innovative formal verification solutions.
* Understanding of application processors, Instruction Set Architectures (ISA), Memory Consistency Models (MCM), or Cache Coherence protocols is desirable but not required.
* Exposure to ARM architectures is also desirable but not necessary.
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