Senior Design Verification Engineer
Find out exactly what skills, experience, and qualifications you will need to succeed in this role before applying below.
Cambridge,/ Bristol England, United Kingdom
Our client can be described as "Developing Foundational Technologies for Chiplet Based Semiconductor Design". They are an early-stage startup, pioneering technologies for the emerging multi-chiplet system-on-package paradigm. Their mission is to enable the next wave of growth in the semiconductor space, and theyre looking for passionate individuals to join a seasoned and dynamic team.
Senior D esign Verification engineer Responsibilities:
* Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems
* Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards
* Collaborate with software teams to define and implement configurable test benches
* Work with design teams test plans, failure debug, coverage, etc.
Qualifications and Preferred Skills
* BS, MS in Electrical Engineering, Computer Engineering or Computer Science
* 8-12 years and current hands-on experience in block-level/IP-level/SoC-level verification
* Proficiency in Verilog, SystemVerilog
* Familiarity with industry-standard EDA tools for simulation and debug
* Deep experience with UVM-based test benches
* Experience with modern programming languages like Python
* Knowledge of Arm AMBA protocols such as AXI, APB, and AHB
* Understanding of Arm CHI protocol is a plus
* Experience on working with IPs for caches, cache coherency, memory subsystems, interconnects and NoCs
* Experience with formal verification techniques, emulation platforms is a plus
* Excellent problem-solving skills and attention to detail
* Strong communication and collaboration skills
Contact:
Uday
Mulya Technologies
muday_bhaskar@yahoo.com