My client is developing a new RISC-V product family. They have a fantastic technical pedigree; they invest heavily in verification methodology research and only hire the best.
They're looking for a Staff Verification Engineer.
Principal Verification Engineer
Responsibilities:
* Develop and execute verification plans in collaboration with design and systems teams.
* Create and maintain testbenches using SystemVerilog, UVM.
* Work closely with RTL designers to understand architectural intent and corner cases.
* Write and review functional coverage models to ensure complete design verification.
Requirements:
* Extensive experience with SystemVerilog and UVM.
* Understanding of good testbench design and theoretical.
* Good scripting in Python/C++ is desirable
Apply to learn more!