🚀 Hiring: Senior Verification Engineer
My client is looking for an experienced Senior Verification Engineer to join their team and help drive high-quality IP verification.
In this role, you’ll own SystemVerilog-UVM testbench development, create coverage-driven verification strategies, and work closely with design teams to debug and deliver robust solutions.
✅ 8+ years in verification
✅ Strong SystemVerilog & UVM experience
✅ Passion for problem-solving and teamwork
If you enjoy building scalable verification environments and making an impact on cutting-edge designs, I would love to hear from you!