Desired Profile :
* Bachelor's / Master's degree in engineering from EEE / E&C with expertise in ASIC DFT
* Define and implement DFT architecture for SoC / ASIC designs
* Perform scan insertion and scan chain stitching
* Develop and validate ATPG patterns for stuck-at, transition, bridge, and path delay faults
* Implement and verify MBIST / memory repair solutions
* Perform DFT rule checks (DRC) and resolve violations
* Support JTAG / boundary scan / IEEE 1149.1 implementation
Run and debug Gate Level Simulations (GLS) for DFT patterns
* Analyze and improve test coverage, pattern count, and test time
* Work closely with design, verification, physical design, and silicon validation teams
* Support post-silicon bring-up and failure analysis
* Create DFT documentation, methodology, and best-practice flows.
VISA SPONSORED FOR MALAYSIA
SEMICONDUCTOR : ASIC PHYSICAL DESIGN ENGINEER
Desired Profile :
* Bachelor's / Master's degree in engineering from EEE / E&C with expertise in ASIC PD
* Experience in Top / Block level ASIC PnR implementation (RTL to GDSII).
* Tape-out experience in lower nodes like 3nm, 5nm, 7nm, 10nm and above.
* Hands-on experience in Synthesis, Floor planning, Placement, Clock tree synthesis, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification (DRC/LVS/DFM, chip finishing) and Sign Off.
* Excellent communication and presentation skills, experience in collaborating with global teams.
* Experience in hierarchical designs and/or Low Power implementation is an advantage.
* Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics tool set.
* Must be an initiative-taker and be able to drive tasks independently and efficiently to completion.
* Ability to provide mentorship and guidance to junior engineers and be an effective team player.
* Expertise in Cadence Innovus, Tempus, Calibre
VISA SPONSORED FOR MALAYSIA
SEMICONDUCTOR : ASIC PHYSICAL VERIFICATION ENGINEER
Desired Profile :
* Bachelor's / Master's degree in engineering from EEE / E&C with expertise in ASIC PV
* Expertise in physical verification with full signoff ownership
* Expertise in DRC, LVS and ESD verification methodologies
* Expertise in Calibre, ICV (IC Validator) or Pegasus
* Expertise in foundry DRM : able to read, interpret, and implement complex rule decks
* Expertise in advanced nodes 4nm and below
* Expertise in using AI agents to drive automation across verification flows and tapeout signoff
Job Specs :
* Own and execute full-chip DRC, LVS, ESD, and antenna signoff using Calibre, ICV, or Pegasus
* Develop, maintain, and optimize physical verification flows for advanced node SoC and 3D IC designs
* Interpret and implement foundry Design Rule Manuals (DRM) — translate rule updates into verified flow changes
* Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs
* Perform ESD verification — validate protection strategies, current paths, and CDM/HBM compliance
* Drive tapeout readiness by coordinating signoff across block and top-level design teams
* Engage directly with foundry teams to resolve DRM ambiguities and waiver requests
* Leverage AI agents to automate rule deck validation, violation triage, and signoff reporting workflows
SEMICONDUCTOR : ASIC STA & SYNTHESIS ENGINEER
Desired Profile :
* Bachelor's / Master's degree in engineering from EEE / E&C with expertise in ASIC STA / SYNTHESIS
* Timing analysis and logic synthesis of digital designs. The role focuses on achieving timing closure and optimizing design performance, power, and area.
* Perform RTL synthesis using industry-standard tools
* Should be capable to analyze and run LEC to ensure gate level netlist matches the original RTL
* Run Static Timing Analysis (STA) and identify timing violations
* Fix setup and hold violations across different corners/modes
* Work on constraints development (SDC creation and validation)
* Analyze timing reports and improve design quality
* Collaborate with RTL, DFT, and Physical Design teams
* Support timing closure during implementation and signoff
* Strong understanding of digital design fundamentals
* Knowledge of synthesis and STA flow
* Familiarity with timing concepts (setup, hold, skew, latency)
* Experience with EDA tools (Experience with EDA tools - (Genus, Tempus)
VISA SPONSORED FOR MALAYSIA
SEMICONDUCTOR : ASIC VERIFICATION ENGINEER
Desired Profile :
* Bachelor's / Master's degree in engineering from EEE / E&C with expertise in ASIC Verification
* Expertise in DDR / Ethernet / PCIe protocol
* Expertise in working on system Verilog assertions & test benches
* Expertise in working on OVM / UVM / VMM based verification flow
* Good knowledge in gate-level simulation, and Scripting languages like Python, TCL
SEMICONDUCTOR : DIRECTOR, ANALOG CIRCUIT DESIGN
ACTIVE REQUIREMENT
Work Expertise : 15+ years
Desired Profile :
* Bachelor's / Master's degree in engineering from EEE / E&C with expertise in mixed-signal or CMOS circuit design
* Expertise in analog blocks like power management DC-DC convertor, LDOs
* Expertise in designing ADC / DAC/ PLLs or Experience in simulation or characterization of IO cells
* Design and architect CMOS analog and mixed-signal integrated circuits
* Simulate designs with state-of-the-art CAD tools
* Document designs and simulation results
* Expertise with high-speed SERDES circuits
* Knowledge of layout issues
* Expertise with circuit simulators (HSPICE, Spectre, etc)
* Expertise with Cadence Design Environment is an asset
* Expertise in PERL and UNIX shell scripting languages
* 15+ years of experience must include 10+ years of expertise in managing and leading mixed signal design teams across different continents
* Expertise in leading business strategy in the VLSI / Semiconductor Services / foundry business industry
* Expertise in managing end to end projects including tape outs
* Must be willing to travel at short notice, relocate as per business needs
* Must be willing to work onsite (customer premises) as per business needs.
* Prior expertise in scaling large teams in services industry for the same technical domain is mandatory
Job Specs :
* Responsible for meeting delivery, revenue, operational, customer satisfaction targets and team management
* Hire and manage high caliber technical teams across GCC, ODC and onsite
* Develop, Drive high quality business / technology strategy and oversee the translation of this strategy into tactical action
* Uphold the organization's culture and long term missions
* Liaise and negotiate with various partners around the world to bring in new partnership.
* Synergize all company's resources and talents for the growth of company's business
* Oversee all sectors and fields of the business to ensure the company's competitiveness
* Provide leadership, direction, major decision making and resolution support to operations, projects and staff.
* Build strategic business partnerships and execute these opportunities through collaboration with external partners
SEMICONDUCTOR : DIRECTOR, ASIC PHYSICAL DESIGN
ACTIVE REQUIREMENT
Work Expertise : 15+ years
Desired Profile :
* Expertise in ASIC PD.
* Expertise in EDA synthesis, APR, STA tools and methodologies
* Expertise in one or more of the following tools ICC, ICC2, Innovus, Olympus
* Working knowledge of one or more of the following tools Primetime, Calibre, and Red hawk
* Expertise in working with multi modes and multi corners STA
* Working Knowledge of multiple power planes and multiple VT libraries
* Basic domain knowledge of EM, IR, RV analysis, Noise and Formal Equivalence Verification
* Good at scripting languages PERL, TCL, shell
* Expertise in EDA tools for the design and implementation of 100 ~ 400 million gate integrated circuits in 12nm* / 7nm* / 5nm / 3nm / 2nm process technologies
* Worked on at least 2 tape ins of moderate to high speed designs with multiple power planes
* Debug, fix, and validate pre- and post-silicon IP/sub-system logic issues and bugs
* Expertise in one or more of the following circuit design fields is an advantage: clock tree optimization, Timing analysis, and Power optimization
* Expertise in making ECOs both Metal and logic level
* Expertise in DRC and LVS cleanup of designs during sign off
* 15+ years of experience must include 10+ years of expertise in managing and leading ASIC PD technical teams across different continents
* Expertise in leading business strategy in the VLSI / Semiconductor Services / foundry business industry
* Expertise in managing end to end projects including tape outs
* Must be willing to travel at short notice, relocate as per business needs
* Must be willing to work onsite (customer premises) as per business needs
* Prior expertise in scaling large teams in services industry for the same technical domain is mandatory
Job Specs :
* Responsible for meeting delivery, revenue, operational, customer satisfaction targets and team management
* Hire and manage high caliber technical teams across GCC, ODC and onsite
* Develop, Drive high quality business / technology strategy and oversee the translation of this strategy into tactical action
* Uphold the organization's culture and long term missions
* Liaise and negotiate with various partners around the world to bring in new partnership.
* Synergize all company's resources and talents for the growth of company's business
* Oversee all sectors and fields of the business to ensure the company's competitiveness
* Provide leadership, direction, major decision making and resolution support to operations, projects and staff.
* Build strategic business partnerships and execute these opportunities through collaboration with external partners
SEMICONDUCTOR : DIRECTOR, ASIC VERIFICATION
ACTIVE REQUIREMENT
Work Expertise : 15+ years
Job Specs :
* Expertise in Functional Verification
* Expertise in working on system Verilog assertions & test benches
* Expertise in working on OVM / UVM / VMM based verification flow
* Expertise in working on ARM processor
* Expertise in working on AMBA bus protocols (AXI, AHB, APB)
* Expertise in CXL or PCIe or UCIe Protocol Verification
* Expertise in simulation tools (VCS, ModelSim, Questa)
* Expertise in driving Verification Strategy, writing Test Plan, developing Test Bench, Test cases.
* Expertise in analysing Code Coverage, Functional Coverage and Assertions.
* Expertise in verification of complex SoCs.
* Expertise in Test Plan creation and Verification technologies like Code Coverage, Functional coverage, assertion based verification.
* Expertise in Verification of complex datapath, DSP based ASICs
* 15+ years of experience must include 10+ years of expertise in managing and leading ASIC DV technical teams across different continents
* Expertise in leading business strategy in the VLSI / Semiconductor Services / foundry business industry
* Expertise in managing end to end projects including tape outs
* Must be willing to travel at short notice, relocate as per business needs
* Must be willing to work onsite (customer premises) as per business needs
* Prior expertise in scaling large teams in services industry for the same technical domain is mandatory
Job Specs :
* Responsible for meeting delivery, revenue, operational, customer satisfaction targets and team management
* Hire and manage high caliber technical teams across GCC, ODC and onsite
* Develop, Drive high quality business / technology strategy and oversee the translation of this strategy into tactical action
* Uphold the organization's culture and long term missions
* Liaise and negotiate with various partners around the world to bring in new partnership.
* Synergize all company's resources and talents for the growth of company's business
* Oversee all sectors and fields of the business to ensure the company's competitiveness
* Provide leadership, direction, major decision making and resolution support to operations, projects and staff.
* Build strategic business partnerships and execute these opportunities through collaboration with external partners
SEMICONDUCTOR : HEAD, TECHNOLOGY INITIATIVES & SOLUTIONS
ACTIVE REQUIREMENT
Work Expertise : 15+ years
Desired Profile :
* Bachelor's / Master's degree in engineering from EEE / E&C
* Expertise in managing and leading technical teams across different continents
* Expertise in leading business strategy in the VLSI / Semiconductor Services / foundry business industry
* Expertise in managing end to end projects including tape outs
* Must be willing to travel at short notice, relocate as per business needs
* Must be willing to work onsite (customer premises) as per business needs
* Expertise in working on any of the following technologies is mandatory :
* ANALOG MIXED SIGNAL LAYOUT - finfet / high speed / planar technology nodes
* ANALOG DESIGN - data converter / power management / pll
* ANALOG VERIFICATION
* ASIC PHYSICAL DESIGN
* ASIC RTL DESIGN
* DFT DESIGN - jtag / mbist / lbist / scan
Job Specs :
* Responsible for meeting delivery, revenue, operational, customer satisfaction targets and team management
* Hire and manage high caliber technical teams across GCC, ODC and onsite
* Develop, Drive high quality business / technology strategy and oversee the translation of this strategy into tactical action
* Uphold the organization's culture and long term missions
* Liaise and negotiate with various partners around the world to bring in new partnership.
* Synergize all company's resources and talents for the growth of company's business
* Oversee all sectors and fields of the business to ensure the company's competitiveness
* Provide leadership, direction, major decision making and resolution support to operations, projects and staff.
* Build strategic business partnerships and execute these opportunities through collaboration with external partners
* Resource must be a citizen of India residing across any states / UT's of India
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