We are seeking an experienced Digital Verification Lead Engineer to drive verification strategy, lead multi-site teams, and contribute to the development of cutting-edge semiconductor products.
This role can be based out of the following locations: Lausanne (Switzerland), Reading/Northampton (UK), Dortmund (Germany), or Copenhagen (Denmark).
Key Responsibilities
* Lead digital verification activities across assigned projects
* Provide technical leadership, guidance, and mentoring to team members
* Develop comprehensive verification plans from design specifications
* Plan and schedule project tasks, assigning and tracking workloads across the team
* Define and implement verification methodologies, including standardized debug flows
* Participate in design and peer reviews to ensure robust design quality
* Maintain and enhance the verification environment; track, manage, and close design bugs
* Collaborate closely with design engineers on verification and validation of circuit designs
* Apply state-of-the-art tools, techniques, and technologies to verification activities
Required Skills
* Excellent communication skills and strong team-oriented mindset
* Proficiency in scripting and experience with regression setup and management
* Deep knowledge of simulation and verification environments, including advanced debugging techniques
* Experience with Gate-Level Simulation flows and debug
* Strong understanding of metrics-driven verification, including planning and coverage closure
* Hands-on experience developing test benches using modern verification methodologies
* Experience with third-party VIP and test development (preferred)
* Experience with emulation platforms and/or FPGA prototyping (a plus)
* Exposure to Assertion-Based Verification (a plus)
Experience
* 7+ years in the semiconductor industry
* Proven experience leading and managing teams across multiple locations
* Strong track record verifying complex digital designs, ideally in high-volume applications
* Ability to balance quality, performance, and schedule trade-offs
* Experience with constrained-random test bench development
* Familiarity with SerDes and high-level protocols (e.g., PCIe, USB, DisplayPort) is advantageous
* Solid background in digital verification, including UVM
* Ability to coordinate and manage external subcontractors to scale verification efforts
Education
* Bachelor’s degree (or higher) in Electronics, Electrical Engineering, or a related discipline
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