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As a Lead System Design Architect, you will spearhead the development of advanced compute system architectures, shaping long-term technology strategies and ensuring designs meet stringent efficiency and performance goals. Collaborating with cross-functional teams, you will explore emerging trends, define system specifications, and foster innovation in hardware for compute-intensive workloads, contributing to transformative technologies in embedded and edge applications. Ultimately you will deliver next-generation embedded and edge compute platforms - RISC-based, power-awareness, and latency focused.
ROLE PROFILE:
* Architect scalable SoCs featuring programmable compute clusters (open-standard RISC-V or ARM-compatible), advanced AXI4-style interconnects, and multi-domain UPF power gating.
* Translate market signals into silicon roadmaps with quantifiable PPA targets.
* Author & sign-off system-level specs, RTL hand-off, and KPI dashboards.
* Drive PPA trade-offs through data-driven analysis (Synopsys Fusion Compiler, Cadence Genus / Innovus, PrimeTime STA).
* Integrate signal-processing / ML kernels via hardware-software co-design; validate on Xilinx Versal-class FPGA prototypes.
* Verify with UVM-based, constraint-random testbenches, formal equivalence, and metrics-driven coverage closure.
* Evangelize architecture vision to executives, OEMs, and ecosystem partners.
* Secure IP—champion novelty disclosures and patent filings.
Technical Stack
* Verification: UVM, SystemVerilog Assertions, JasperGold / VC Formal.
* Power: UPF/CPF-driven flows, dynamic voltage-frequency scaling.
* Automation: Python & TCL scripting for flow orchestration, data mining, and regressions.
* Version Control: Git-based, trunk-oriented CI/CD.
Must-Haves
* Proven ownership of high-performance compute or networking silicon.
* Expert command of RTL design, PPA optimization, and cross-functional leadership.
* Fluency communicating complex trade-offs from lab bench to boardroom.
Nice-to-Haves
* Real-time, safety-critical, or ultra-low-latency workload pedigree.
* PhD or published research in heterogeneous compute architectures.
* ISO 26262 / DO-254 safety lifecycle know-how.
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