Company Description
Rigpa is an exciting fabless chip design start-up focusing on the next-generation AI ASIC chips. These chips are designed to accelerate future AI applications at 10x faster speed with a fraction of the power.
As we hit the limits of speed, cost, and scale on today's chips, specialised chips are inevitable. Join us in solving the most important problem in AI.
Role Description
This is a full-time on-site role for a Digital IC Design Verification Engineer at all levels. The role is located in Cambridge or Edinburgh.
We are looking for verification engineers who can ensure the functional correctness of complex AI accelerator designs. You will develop advanced verification environments and drive coverage to ensure first‑silicon success.
Qualifications
* Experience in Digital IC Design Verification
* Skills in digital design verification techniques such as Systemverilog, UVM, C/C++, Python, etc
* Ability to collaborate effectively within a team and work on-site
* Strong problem-solving skills and attention to detail
* Bachelor's or Master's degree in Electrical Engineering or related field
* Experience in AI chip design verification is a plus
Join our silicon design team working on cutting‑edge AI ASIC. You will help define and implement the digital microarchitecture of the next-gen AI chip.
Key responsibilities
* Collaborate with design teams to develop verification strategies for AI accelerator blocks and entire SoC subsystems.
* Build SystemVerilog/UVM testbenches, including test plans, monitors, checkers and constrained‑random stimulus.
* Perform coverage‑driven and assertion‑based verification; measure functional and code coverage to identify gaps and close them.
* Debug complex hardware–software interactions, reproduce silicon bugs in simulation and collaborate with architecture, RTL and software teams to resolve issues.
* Develop verification frameworks that scale from unit‑level simulation to emulation and post‑silicon validation, including high‑level models and test generators.
Ideal qualifications
* 5+ years of experience in digital design verification for CPU/GPU/NPU or AI accelerator IP.
* Expertise in SystemVerilog, UVM and scripting languages (Python/C++/Perl/TCL).
* Solid understanding of computer architecture, memory hierarchies and standard bus protocols (AMBA/AXI, NoC).
* Experience with formal verification and assertion‑based methodologies; knowledge of low‑power verification techniques is desirable.
* Ability to work in a fast‑paced startup environment and collaborate across hardware and software teams.
Join us in building the most advanced hardware for superintelligence.
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