Timing-Locked Acquisition and Packet Framing Location: Remote, UK preferred
Considering applying for this job Do not delay, scroll down and make your application as soon as possible to avoid missing out.
Compensation: Conditional growth shares in Xeroth AI Limited. Current hurdle price £8.89 per share. No cash for this stage.
About Xeroth Xeroth is a radar and AI startup addressing human wildlife conflict, starting with the wire-snare bushmeat poaching crisis. We are building snareSAR, an airborne sensing pod that fuses SAR, optical, and navigation data to expose hidden metal snares and help remove them at scale.
Project status The post-processing stage is already in place.
Hardware stage, RF chain on Koheron ALPHA250-4 with Zynq-7020, is almost complete.
Sample-rate path to 31.25 MSPS is implemented with a buildable Alpine Linux SD image. You will not redo this work.
The downstream stages are already staffed and will start once this stage is accepted:
Stream Transport and Edge Ingest
Flight Integration and Relay Services
Ground Ingest, Calibration, and Health Telemetry
Your stage and mission Own the Timing-Locked Acquisition and Packet Framing stage. Turn a working capture path into a flight-ready, deterministic acquisition engine that the rest of the system can trust.
You will deliver: PPS-locked timebase: 64-bit counter latched on each 1 PPS, AXI-readable registers, proven stable lock.
Deterministic PRF engine: Fixed PRF phase-aligned to PPS. Gate to a fixed IQ sample count per pulse. One packet per pulse with zero drift over long runs.
Packet header framing: Compact metadata header with magic value, monotonic pulse index, latched time counter, and fixed sample count. AXI-Stream to DMA for PS handoff.
AXI control for RF switching: Manual and Automatic modes, with Automatic toggling on each PRF tick.
Acceptance proof: Timing-clean bitstream with reproducible builds, logs and test utilities showing PPS stability, PRF lock, correct framing, and sustained packet integrity.
Handoff notes: Clear memory map, register set, packet spec, and test procedure for the next engineer.
What great looks like: You have shipped PPS-locked counters, PRF generators, gated acquisition, and AXI control on Zynq or similar.
You treat timing closure, jitter budgets, and long-run drift as first-class deliverables.
You document precisely and hand off cleanly.
Requirements Strong FPGA development on Xilinx with Vivado, AXI-Stream, AXI-Lite, DMA to ARM.
External PPS integration and phase alignment experience.
High-rate packetisation in fabric with simple, robust framing.
Nice to have: SDR or radar background, CIC and FIR chains, PS-PL work on embedded Linux.
Why join Your design becomes the heartbeat of an airborne radar that protects wildlife.
Equity upside in a focused mission-driven startup. Conditional growth shares vest on accepted milestones. Hurdle price is £8.89 per share.
TPBN1_UKTJ