About Analog Devices
Analog Devices, Inc. (NASDAQ: ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at and on and.
Senior Design Verification Engineer
The Data Center and Energy team at Analog Devices is seeking SENIOR DESIGN VERIFICATION ENGINEER. The successful candidate will join a talented and motivated multi-disciplinary team, contributing to the design verification of impactful and innovative analog and mixed-signal products and technologies, and collaborating with internal technology groups and external technology vendors to establish and continuously improve a best-practice development methodology for the team.
Requirements:
1. Bachelor’s/Master's degree in electronics engineering or equivalent with 4+ years of experience
2. Contributions to full chip level design verification of mixed signal devices
3. IC top-level DMS SV/UVM verification, Object-Oriented and Randomized Verification, as well as Gate Level Simulation
4. Modelling and validation of analog blocks (RNM, Verilog-AMS)
5. Proficiency with Cadence tool suite, such as Xcelium/IMC/Virtuoso etc.
6. Verification planning tools (ePlanner/vManager) and scripting languages (Shell/TCL/Perl/Python)
7. Experience with multiple clock and power domains
8. Strong verbal and written communication skills and ability to collaborate with a global team
Role:
9. Contribute to the pre-silicon verification of impactful, innovative mixed-signal products, working with a team of verification and design engineers
10. Bridge the verification and validation environments, supporting post-silicon validation.
11. Execute for 100% verification coverage, combining DMS and AMS, top-level, IP-level, and Formal Analysis.
12. Continuously improve verification flows, methodologies and models for the team
Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days