As part of EnSilica’s ongoing expansion, we are looking to strengthen our ASIC Digital Design team. We are looking for bright candidates who have an enthusiasm and aptitude for working in this vital part of our business. You will have a strong academic record, 15 years experience in industry working on ASIC developments and IP design, with at least one successful project as Technical Lead, and one successful project as SoC Architect. You will possess a broad understanding of the IC design flow, strong ‘hands-on’ technical skills together with excellent communication skills and a desire to work in a customer facing organisation. Your Key Responsibilities Lead FE microarchitecture and FE design development of ASIC or complex IPs. Functional specification, SoC microarchitecture, RTL design of blocks and integration layers Take full-flow ownership of all stages of the digital specification to RTL design flow, for complex ASIC blocks or full-chip Work closely with our customers and other EnSilica teams to deliver projects on-time and to the required quality levels Setup, run and maintain EDA tool flows, as needed, for each stage of the FE design flow Keep up to date with all aspects of advanced ASIC FE design methodology and best-practise to ensure that EnSilica’s expertise and service quality are at their top for each customer project Your Key Skills and Experience Essential 1st or 2.1 Electronics, Physics or relevant subject from a Tier 1 group University 15 years experience working in IC Development with a deep understanding of all aspects of ASIC FE design, from specification to RTL, and with a basic understanding of RTL to tape out flow Specific expertise in the following technical areas : ASIC microarchitecture: Interconnect requirements and design, CPUs, integration requirements of the main chip interfaces (DDR, PCIe, JESD204, ), pinout and ballout design, die size and power consumption estimation, 3rd party IP selection Sound knowledge of SoC interconnect protocols, at least the Amba AHB, APB4, one of the Amba AXI (AXI3, AXI4, AXI4-Lite, ACE, AXI5, AXI5-Lite,), and AXI-stream Strong RTL Design skills (VHDL or Verilog, System Verilog) Strong Lint, CDC, RDC analysis skills Functional verification – ideally a good knowledge of System Verilog and the use of techniques such as assertions and coverage driven verification ASIC implementation skills (synthesis, DFT, timing closure) Experience to lead complex IP design and full ASIC design, from specification to full RTL Desirable Knowledge of UPF syntax to describe power intent Knowledge of several chip level communication interfaces is a significant advantage (I2C, SPI, UART, JTAG, …) Experience in CPU selection, through benchmarking, is a real plus About You Strong communication and presentation skills, which enable you to interface easily and effectively with cross-functional stakeholders in an international environment. You think holistically, are creative, and have a quick grasp, which enables you to maintain an overview in complex situations and make well-founded decisions. You are a problem-solver and work independently and with drive to achieve results. The ability to engage all members of a diverse team towards a shared objective. You have proven leadership abilities with strong team management skills, able to motivate, coach and develop team members. You are results-oriented with a strong sense of ownership and accountability A team player, ideally with experience collaborating within the international, cross-functional environments. Adaptable and wiling to embrace change. Happy to take ownership of issues and provide suitable solutions. What can you expect from us? Private Medical healthcare, salary sacrifice pension scheme (matched up to 5%), 26 days annual leave, life assurance, discretionary annual bonus, share option scheme, hybrid and flexible working Position Specifics This role is hybrid, our guideline is for 3 days in the office Some occasional travel may be required to another EnSilica office Applicants must have the right to live and work in the UK