Digital IC Layout Engineer – Contract (Inside IR35)
* Location: On-site / Swindon
* IR35: Inside IR35
* Contract: Long-term, ongoing programme
* Start: ASAP
The Opportunity
A global semiconductor design organisation is looking for an experienced Digital IC Layout Engineer to support high-volume, production silicon across advanced power and mixed-signal platforms.
You’ll join a mature, well-established layout team working closely with ASIC and digital design engineers on complex SoCs, PMICs, and power management devices used in automotive, industrial, IoT, and data-centric applications.
This is a hands-on layout role within a highly structured, best-practice-driven environment.
Key Responsibilities
* Digital and mixed-signal IC layout from schematic to tape-out
* Place & route, timing-driven layout, and constraint-based design
* DRC / LVS / ERC sign-off and layout optimisation
* Collaboration with ASIC, verification, and physical design teams
* Support silicon revisions, debug, and yield improvements
Required Experience
* Strong background in Digital IC Layout / Physical Design
* Experience using Cadence Virtuoso and/or Innovus
* Solid understanding of timing, clocking, scan chains, and constraints
* Familiarity with advanced verification flows (DRC/LVS/QRC/Calibre or similar)
* Ability to work on-site in Swindon
Why This Contract?
* Inside IR35 with long-term programme stability
* Work on shipping silicon generating real revenue
* Highly experienced leadership and established design processes
* Immediate impact within a high-performing layout organisation
If you’re a Digital IC Layout Engineer looking for a stable, technically strong contract within a world-class semiconductor environment, this is a great opportunity to step into.
Apply now or message for a confidential discussion.