Senior Mixed Signal Verification Engineer
A Senior Mixed Signal Verification Engineer will join an exciting Semiconductor scale‑up to undertake digital, mixed signal and analog verification related to high‑speed SerDes designs. The company is leading the development of high‑speed and energy‑efficient chip‑chip link solutions, revolutionizing wired connectivity worldwide.
To be considered for an interview, please ensure your application fully matches the following job specifications. The role requires a degree qualification, a minimum of 10 years of verification experience, strong scripting skills, and extensive experience with Cadence tools.
* Extensive experience in digital/mixed signal/analog verification with test bench design, connect modules, and electrical/discrete partitioning
* Good scripting skills
* Cadence APS, SpectreX / digital solver expertise
* System Verilog Assertions
* Cadence Virtuoso Framework: schematic editor, assembler, AMS
* High‑speed communication systems such as SerDes
* Solid digital verification background with some Specman/SV UVM exposure and/or analog verification background
A competitive salary will be offered, along with hybrid working arrangements, shares, and numerous benefits.
#J-18808-Ljbffr