VHDL, Verification, Verilog, RTL, UVM, SystemVerilogA leading engineering company is seeking an experienced Principal Verification Engineer to strengthen their team and lead the growth of the verification business. With a focus on high level verification techniques, including Universal Verification Methodology UVM and SystemVerilog, this role offers the opportunity to lead critical customer and internal projects, develop verification strategies, and enhance test environments. Experience 10 years of industry experience in verification engineering. Expertise in UVM, SystemVerilog, VHDL or Verilog RTL, and verification infrastructures. Verification tools Mentor Questa, Cadence Incisive and low power verification UPF. 1st or 2.1 degree in Electronics, Physics, or Computer Science from a Tier 1 University. Role Lead verification efforts on various projects using advanced techniques constrained random, coverage-driven, assertion-based, formal methods. Develop comprehensive verification strategies and test plans. Collaborate closely with customers to build strong, long term relationships. Drive the adoption of new verification methodologies within the team. Provide mentorship and leadership to junior engineers.