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Job Overview
Responsible for layout design and management of analog/mixed signal IP consisting of high-speed and high accuracy analog front ends, including ADC, DAC and PLL. The candidate is expected to lead and manage the delivery of complex analog IP with tasks such as floorplanning, bump map, IO planning, LEF, LVS, ERC, DRC, and antenna checks.
Responsibilities
* Lead and manage layout design and delivery of analog/mixed signal IP.
* Develop and optimize floorplan, bump map, IO planning, and related design checks (LEF, LVS, ERC, DRC, antenna checks).
* Manage project schedules and track progress against the project plan.
Minimum Qualifications
* Bachelor’s degree or equivalent in EE or training in layout design.
* Industry experience of 10+ years in layout design of analog/mixed signal circuitry.
* Direct layout experience in at least two of the following: high-speed ADC, DAC, high-performance phase-locked loops (LC tank-based designs preferred).
* Experience in 16nm or below technology is a must.
* Past active participation in at least 2 successful complex analog silicon projects involving one or more of the above areas.
Preferred Qualifications
* Deep understanding of floor planning, matching, noise isolation, power supply and signal integrity.
* Project leadership experience on successful complex analog chips.
* Excellent communication skills and ability to work with remote design teams.
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