Senior Verification Engineer RF DSP This role is all about depth. Proper signal-chain verification, not tick-box regression.
What you will be doing
Owning verification of DSP and RF signal-chain blocks using UVM and advanced methodologies
Validating complex algorithms including FFT, FIR and channelisers
Building and maintaining class-based testbenches with VIP integration
What you need
Strong UVM and constrained-random verification experience
Proven DSP verification background
Python scripting and CI CD workflows
Git proficiency
Experience with Adaptive SoC flows using Vivado and Vitis
MATLAB experience highly desirable
Senior Verification Engineer High-Speed Networking This one is about performance, scale and coverage closure under pressure.
What you will be doing
Verifying high-speed connectivity IP in class-based UVM environments
Driving test plans, coverage closure and sign-off
Integrating and managing VIP for complex networking protocols
What you need
Advanced UVM and constrained-random verification expertise
Hands-on experience with 100Gb Ethernet, PCIe Gen5 and AMBA AXI
Python and CI CD-based regression flows
Git proficiency
Adaptive SoC design flow experience
Understanding of embedded processor co-simulation and SoC debug
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