Application Specific Integrated Circuit Design Engineer
Application Specific Integrated Circuit Design Engineer
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Business Manager - Semiconductor Division
Cambridge
This is a great opportunity for a Digital ASIC Engineer to join a leading semiconductor company based in Cambridge but HQ’d in Silicon Valley. They supply high-performance components for high-voltage power conversion. Their products are used in consumer electronics, appliances, and LED lighting.
This is a unique opportunity that offers exposure to the full ASIC digital design flow. You’ll have the chance to build and refine a broad range of skills, including Synthesis, DFT, and Floorplanning.
This role is ideal for someone eager to be part of a collaborative team and open to learning new skills. It’s not a position focused on a narrow or repetitive task — instead, it offers variety and the chance to contribute across multiple areas of the design process.
As a Digital ASIC Design Engineer, you should:
* MSc/MEng or PhD in Electronics Engineering or related subject.
* Minimum 3 years’ experience in digital IC design.
* In depth knowledge and understanding of best-practice digital design methods.
* Be familiar executing designs via a fully synthesised digital design flow with RTL and logic synthesis.
* Verilog and SystemVerilog experience.
* Be familiar with the use of constraints and the automatic place-and-route flow for the physical design.
* Have experience of design techniques for optimising digital power consumption.
Main Responsibilities:
* Development of functional digital blocks and contribution to complete mixed signal ASICs from definition to full production maturity.
* Complete RTL design in SystemVerilog of digital functions to meet all specification requirements.
* Create suitable block-level test benches for comprehensive verification of all digital blocks.
* Create suitable behavioural models and top-level test benches for comprehensive verification and regression of all system-level functions and production test functions.
* Complete digital synthesis with suitable physical constraints to meet all PPA requirements.
* Define and implement DFT architecture. Perform scan insertion, ATPG and insert test points to achieve the required test coverage.
* Define digital layout floorplan, oversee digital place-and-route, and ensure post-layout timing closure.
* Generate all necessary design documentation and participate in design reviews.
* Contribute to Technology Process and Design Methodology improvements.
As a top company, they offer a variety of different benefits including an employee stock purchase scheme, private healthcare, group life scheme + more!
For more info, please contact Rachel Mason at IC Resources
Seniority level
* Seniority level
Mid-Senior level
Employment type
* Employment type
Full-time
Job function
* Industries
Semiconductor Manufacturing and Computer Hardware Manufacturing
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