Job Description:
Role: Senior IP Design EngineerType: ContractLocation: Belfast, UK Hybrid
Job details:Design high-performance IP targeting FPGA/Adaptive SoC technology using SystemVerilog RTL. Deliver synthesis-ready designs meeting timing and integration requirements.
Key Skills:SystemVerilog RTL design100Gb Ethernet, PCIe Gen5, AMBA/AXIDeep understanding of FPGA/Adaptive SoC design flow including P&R and timing closureVivado/Vitis expertisePython/Tcl scriptingGit & CI/CD experience
JBRP1_UKTJ