I am seeking several ASIC Design Engineers to join a fast-moving, venture-backed semiconductor startup founded by serial entrepreneurs with a vision to accelerate intelligent computing in the emerging chiplet era. This is an exciting time to be one of the early Engineers into a UK IP Team. Their focus is on unified fabric solutions for both single-die and multi-die systems. They design and license disruptive IP for semiconductor chips. I am seeking ASIC Design Engineers with strong expertise in microarchitecture and RTL coding. You must come from a background in IP Design. You will play a key role in shaping company technology portfolio, contributing both technical depth and creativity to solutions. Responsibilities Design and develop microarchitectures for highly configurable IPs Implement RTL designs optimised for performance, power, and area Qualifications & Skills BS/MS in Electrical Engineering, Computer Engineering, or Computer Science 5 years’ hands-on experience in microarchitecture and RTL development Strong proficiency in Verilog and SystemVerilog Familiarity with industry-standard EDA tools and methodologies Experience with large, high-speed, pipelined, and low-power designs Deep understanding of on-chip interconnects and NoCs Experience designing IP blocks (Nice to have) IP Block design for caches, coherency, memory subsystems, and interconnects Knowledge of RAS, QoS in fabrics, and PCIe/IO (a plus) Familiarity with Python Any experience with LLM accelerator chips, RISC-V processors, Cache and AMBA protocols will be advantageous. As well as working for a technologically advanced company with fantastic career opportunities, on offer is a competitive base salary and share options and a paid bonus. If you have European working rights, you may also be considered on a remote working basis. For UK Nationals, office location is Cambridge with fully remote and hybrid options also available.