Senior Verification Engineer – High-Speed Networking
We are looking for a Senior Verification Engineer to verify high-speed connectivity IP using UVM and advanced SystemVerilog verification methodologies. The role focuses on functional coverage closure, constrained-random testing, and integration of verification IP (VIP) for next-generation networking protocols.
Key Responsibilities
* Develop and maintain UVM-based verification environments
* Perform constrained-random verification and coverage closure
* Integrate and customize VIP for high-speed interfaces
* Verify protocols including 100Gb Ethernet, PCIe Gen5, and AMBA/AXI
* Automate verification flows using Python and CI/CD pipelines
* Collaborate with design and software teams; support bring-up using Vivado/Vitis
Required Skills
* Strong UVM and SystemVerilog verification experience
* High-speed protocol knowledge: 100GbE, PCIe Gen5, AXI
* Python scripting and Git-based workflows
* Experience with CI/CD in verification environments
* Familiarity with AMD Vivado/Vitis tools