Are you an expert in Design for Test (DFT), and we're looking for a talented Principal DFT Engineer to join our dynamic engineering team in Theale/Bristol. This is a unique opportunity to lead critical DFT implementation for cutting-edge ASIC designs while shaping the future of our DFT practices.
As a Principal DFT Engineer, you will take on a leadership role in delivering DFT (including ATPG) implementation at both the chip and block levels. You will lead DFT strategy, manage the implementation of DFT structures, perform formal checks, debug test pattern mismatches, and ensure timing closure in DFT modes. This role may involve acting as an industry-leading expert in a specific area of DFT or leading a team to deliver complete DFT solutions from architecture to pattern generation.
Key Responsibilities:
* DFT Strategy & Implementation: Lead the DFT work in projects, including the definition of DFT strategy, implementation of DFT structures, and verification of the DFT structures to meet the project's testability requirements.
* DFT Expertise: Serve as an expert in DFT tools and techniques, demonstrating advanced skills in tools from Mentor, Synopsys, or Cadence.
* Complex Problem Solving: Address and resolve complex issues related to DFT, ATPG, timing closure, and ATE chip bring-up, providing solutions to challenges across multiple projects.
* Leadership & Mentorship: Lead DFT design projects and mentor junior engineers, providing guidance in technical aspects and helping to manage the team’s workflow and priorities.
* Customer Interface & Project Management: Act as the main customer interface for DFT aspects of the project, ensuring clear communication and alignment. Take responsibility for managing multiple assignments from different customers and teams.
* Continuous Improvement: Analyse customer feedback and recognise business opportunities. Collaborate with the Sondrel Business Team to push these opportunities forward.
* Technical Contributions: Contribute to technical white papers, present at internal and external conferences, and participate in sales support, such as preparing Statements of Work.
* Team Organisation: Organise and manage teams effectively, setting and adjusting priorities quickly to meet project timelines.
Key Relationships:
Internal:
* Reports to: Regional Engineering Head
* Collaborates with: Engineers, Project Leaders, Sales, Finance, and HR teams
* Supervises: Engineers, Senior Engineers, and Staff Engineers
External:
* Customers: Minimal technical engineer-to-engineer communication
* Suppliers: EDA Tool Vendors, Foundries, and Assembly Houses
Qualifications:
Essential:
* A Bachelor’s degree, Master’s, or PhD in Engineering or a related field.
* Typically 10+ years of experience in the microelectronics field, specifically in DFT.
* Strong Project Management skills.
* Desirable:
* A project management qualification.
* Additional experience in high-level design teams, especially in DFT architecture.
Skills & Experience:
Essential:
* Extensive experience with DFT tools (e.g., Mentor, Synopsys, Cadence) and techniques including:
* IJTAG/Scan/MBIST/BSD/LBIST/Boundary Scan insertion.
* ATPG/TC improvements and pattern generation.
* Pattern simulation (Zdel/SDF) and pattern verification (VCS, NC-Verilog, NC-Sim, ModelSim).
* Diagnosis of ATE failures and silicon bring-up.
* Deep understanding of DFT architecture design and implementation.
* Strong problem-solving skills and ability to lead or collaborate in a DFT team.
* Expertise in managing complex, technical DFT projects.
* Advanced scripting skills in Python, TCL, Perl, Shell, or similar languages.
* Proven ability to evaluate issues, define solutions, and make sound judgments in technical environments.
Desirable:
* Ability to apply advanced knowledge in specific areas of physical design or a broad understanding across multiple sub-functions of DFT.
* Proven capability to contribute to business development and customer engagement.
Attributes:
* Team leader with strong organisational skills and the ability to manage multiple priorities.
* Active listening skills and the ability to motivate a team to work under pressure.
* Excellent attention to detail and high level of self-motivation.
* Strong conflict resolution skills and the ability to quantify risks and estimate engineering effort.
* Ability to think creatively and "outside the box."
Why Aion Silicon?
At Aion, we are committed to advancing the boundaries of digital design. You’ll be leading key DFT projects in a collaborative, innovative, and growing team. This is a fantastic opportunity to have a direct impact on both technical and business outcomes while working on cutting-edge ASIC designs in a global environment.
If you are a seasoned Principal DFT Engineer with a passion for leading technical teams and projects, we would love to hear from you.