Overview
Staff Engineer, Design Verification at Analog Devices (ADI). The Design Verification Engineer will collaborate with the wider ADI technical community to define, develop and implement verification solutions for mixed signal ICs in the CSS domain, spanning the full development cycle from concept through verification planning, implementation, execution and release to customers.
About Analog Devices
Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, digital healthcare, and more. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI aims to keep customers ahead of whats possible. Learn more at www.analog.com and on LinkedIn and Twitter (X).
Job Description
The charter of ADI’s CSS team is to lead the market in selected technology domains with highly differentiated sensing and signal processing solutions. Current focus areas include Capacitive Sensing, Optical Image Stabilization, Power management and Audio for portable and non-portable consumer systems. This role involves defining, developing and implementing verification solutions for mixed-signal ICs within this market area, covering the entire development lifecycle from concept to product release. The Design Verification Engineer will collaborate with the wider ADI technical community, providing exposure to multiple business units, technologies and products.
Responsibilities
* Verification of complex designs and sub-systems using leading-edge verification methodologies
* Contribute to and influence decisions on methodologies/strategies for design verification
* Develop testbench architectures using UVM or Formal verification approaches
* Define verification plans, functional coverage, tests and verification methodology for block/chip-level verification; collaborate with design teams on plans and closure metrics
* Debug Gate Level Simulation (GLS) and resolve timing violations approved by designers
* Maintain continuous interaction with analog co-simulation and firmware teams
* Mentor and guide junior verification engineers on SoC verification
* Support post-silicon verification activities with design, product evaluation and applications engineering teams
* Lead verification efforts at IP or SoC level, including effort estimation, project scheduling, task assignment and reporting
Qualifications
* Bachelor's or Master’s degree in Engineering (Electronic Engineering) or equivalent
* Experience in both IP and SoC level verification
* Strong knowledge of verification-plan generation, coverage analysis, constrained random techniques, assertion-based and formal verification with SystemVerilog
* Proficient in developing unit and SoC-level testbenches using UVM; integrate block testbenches in chip-level UVM environments
* Demonstrated experience in verification techniques for one or more DSP/Processor subsystems or formal verification
* Excellent debugging and analytical skills
* Proficiency in scripting languages and utilities (Makefile, Python, TCL/tsh, Perl, etc.)
* 5–10 years in ASIC design verification
Additional Preferred Qualifications
* Experience with hardware emulation or FPGA prototyping
* Experience in behavioural modelling of analogue circuits
* Experience in verifying processor-based designs
* Knowledge of interface protocols (AHB/APB/AXI/I2C/SPMI)
* Ability to code test cases in C for processor-based products
* Customer-facing experience as verification lead
* Experience building and leading small verification teams; strong interpersonal and communication skills; proficient English
Export control notice: For positions requiring access to technical data, Analog Devices may require export licensing approval. Applicants may need to undergo an export licensing review process.
Equal opportunity: Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of race, religion, age, origin, sex, sexual orientation, gender identity, or other legally protected status.
Details
* Job Req Type: Experienced
* Required Travel: Yes, 10% of the time
* Shift Type: 1st Shift/Days
Seniority level
* Mid-Senior level
Employment type
* Full-time
Job function
* Engineering and Information Technology
Industries
* Semiconductor Manufacturing
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