The Role
Senior IP Design Engineer
Your responsibilities:
Design high-performance IP targeting FPGA/Adaptive SoC technology using System Verilog RTL. Deliver synthesis-ready designs meeting timing and integration requirements.
Your Profile
Essential skills/knowledge/experience:
•System Verilog RTL design
•100Gb Ethernet, PCIe Gen5, AMBA/AXI
•Deep understanding of FPGA/Adaptive SoC design flow including P&R and timing closure
•Vivado/Vitis expertise
•Python/Tcl scripting
•Git & CI/CD experience