Exciting Semiconductor Company seeks a Senior Digital Physical Design Engineer with expertise in Static Timing Analysis (STA) and Timing / SDC constraints, modern semiconductor process technologies and an experienced user of EDA tools. Generous salary package with Hybrid working. This cutting-edge scale-up Semiconductor Company is revolutionizing the electronics industry, enabling the build of high-speed, low cost, energy efficient scalable AI systems Worldwide. Requirements for the Digital Physical Design Engineer include: * Bachelors / Masters Degree in Electronics, Computer Science or similar. * 5-10 years commercial Physical Design Engineer experience in the semiconductor industry. * Working on modern semiconductor process technologies: 14/16nm, 7nm, 5nm and 3nm. * Expertise in STA and Timing Constraints. * Advanced user of a range of EDA tools. * Experience in SDC verification tools. * Solid understanding of RTL to GDS implementation flow. * Good Scripting skills. The successful Digital Physical Design Engineer will work closely with the Architecture, RTL, DFT and manufacturing teams to ensure right first time high-volume silicon production. You’ll undertake Timing Constraint development and validation; Block and chip level STA, implementation of SDC constraints as well as implanting solutions for STA and supporting IP and chip level integration. To find out more, apply in confidence now...